DocumentCode :
2987369
Title :
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management
Author :
Shareef, M. ; Nair, Pradeep ; Amrutur, Bharadwaj
fYear :
2008
fDate :
4-8 Jan. 2008
Firstpage :
503
Lastpage :
508
Abstract :
This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.
Keywords :
SPICE; SRAM chips; frequency control; voltage control; DVFM control system; HDL; SPICE simulation; SRAM; dynamic voltage management; energy reduction; frequency 100 MHz to 1 GHz; frequency management; voltage 50 mV; voltage 500 mV; voltage frequency control scheme; Clocks; Control system synthesis; Control systems; Delay; Energy management; Frequency control; Hardware design languages; Random access memory; Threshold voltage; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2008. VLSID 2008. 21st International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
0-7695-3083-4
Type :
conf
DOI :
10.1109/VLSI.2008.47
Filename :
4450549
Link To Document :
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