Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

Author

Kannan, S.A. ; Sreeram, N.S. ; Amrutur, Bharadwaj S.

Author_Institution

Indian Inst. of Sci., Bangalore

fYear

2008

fDate

4-8 Jan. 2008

Firstpage

509

Lastpage

514

Abstract

In this paper analytical expressions for optimal V_dd and V_th to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal V_dd and V_th is analyzed. A new gradient based algorithm for controlling V_dd and V_th based on delay and power monitoring results is proposed. A V_dd-V_th controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Keywords

gradient methods; logic design; nanotechnology; voltage control; DVFM controller; EKV model; MPEG decoder; analytical expressions; delay monitoring; gate leakage; gradient based algorithm; logic block; power monitoring; size 65 nm; Algorithm design and analysis; Decoding; Delay; Gate leakage; Heuristic algorithms; Logic design; Monitoring; Predictive models; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2008. VLSID 2008. 21st International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

0-7695-3083-4

Type

conf

DOI

10.1109/VLSI.2008.69

Filename

4450550