An adaptive Viterbi decoder on the dynamically reconfigurable processor

Author

Abe, Shohei ; Hasegawa, Yohei ; Toi, Takao ; Inuo, Takeshi ; Amano, Hideharu

Author_Institution

Dept. of Inf. & Comput. Sci., Keio Univ., Hiyoshi

fYear

2006

fDate

Dec. 2006

Firstpage

285

Lastpage

288

Abstract

In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics´ DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the signal to noise ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long

Keywords

Viterbi decoding; adaptive decoding; microprocessor chips; mobile computing; 4.71 to 9.95 Mbit/s; 423.93 to 1028.97 mW; adaptive Viterbi decoder; adaptive computing; base station; mobile computing; mobile terminal; reconfigurable processor; switching design; Bit error rate; Decoding; Energy consumption; Field programmable gate arrays; Hardware; Mobile computing; National electric code; Throughput; Tiles; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

0-7803-9729-0

Electronic_ISBN

0-7803-9729-0

Type

conf

DOI

10.1109/FPT.2006.270329

Filename

4042451