0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops

This paper describes the architecture and performance of a 0.35 mu, 1 GHZ, CMOS timing generator using array of delay lock loop. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed delay lock loops uses novel multiplexer based dual phase and frequency detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. This greatly reduces the timing jitter, loop locks to both the leading and trailing clock edges as the dual phase and frequency detector along with charge pump converts the phase difference in to voltages. Test results show a timing jitter of less than 20 pS for the DLL (delay lock loop) circuit .The DLL has a dead zone less than 0.01 nS in the phase characteristics and has low phase sensitivity errors. The timing generator is implemented as an array of delay locked loops (Kostamovaara, 2000) which exponentially reduce the locking time. An experimental proto type was simulated at 0.7 mu and 0.35 mu technologies with a supply voltage of 5 V and 3.3 V respectively.