DocumentCode
2987665
Title
ATPG aspects of FSM verification
Author
Cho, Hyunwoo ; Hachtel, Gary ; Jeong, Seh-Woong ; Plessier, Bernard ; Schwarz, Eric ; Somenzi, Fabio
Author_Institution
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
134
Lastpage
137
Abstract
Algorithms are presented for finite state machine (FSM) verification and image computation which improve on the results of O. Coudert et al (1989), giving 1-4 orders of magnitude speedup. Novel features include primary input splitting-this PODEM feature enlarges the search space but shortens the search due to implications. Another new feature, identical subtree recombination, is shown to be effective for iterative networks (eg, serial multipliers). The free-variable recognition feature prevents unbalanced bipartitioning trees in tautological subspaces. Finally, reached set pruning is significant when the image contains large numbers of previously reached states.<>
Keywords
finite automata; logic CAD; logic testing; sequential circuits; PODEM feature; automatic test pattern generation; finite state machine verification; free-variable recognition feature; identical subtree recombination; image computation; iterative networks; primary input splitting; serial multipliers; tautological subspaces; unbalanced bipartitioning trees; Automata; Automatic test pattern generation; Boolean functions; Data structures; Formal verification; Iterative algorithms; Sequential analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129861
Filename
129861
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