An ILP formulation for low power based on minimizing switched capacitance during data path allocation

Power consumption has been established as an important factor in the synthesis of VLSI circuits. However, very little work has been done at the behavior level for power estimation and low power synthesis. We demonstrate how hardware sharing affects the capacitance and transition activity, and hence the power dissipation in the synthesized data paths, and that the power-optimal allocation varies with input characteristics. We present a simulation-based method that measures both intra- and inter-iteration effects of hardware sharing on switched capacitance. This method enables us to accurately capture sufficient information to evaluate allocation options from a switched capacitance point of view. Using the information thus obtained, we formulate allocation as an Integer Linear Programming (ILP) problem with the total switched capacitance in the data path as the objective function. Thus, the decisions of how much hardware sharing should be performed and what allocation is best from the power point of view, are performed optimally for the given model. Experimental results are presented including accurate power measurements made at the switch level