Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators

Author

Nicolle, B. ; Tatinian, W. ; Mayol, J.-J. ; Oudinot, J. ; Jacquemod, G.

Author_Institution

UMR-CNRS-UNSA, Valbonne

fYear

2007

fDate

3-5 June 2007

Firstpage

475

Lastpage

478

Abstract

In this paper, we present a design methodology based on a multi-simulator approach instead of using co-simulation. We based our study on a phase locked loop (PLL) used in RF transceivers for frequency synthesis. We used Simulink as block diagram simulator, ADVance MS (ADMS) as behavioral simulator and Eldo as transistor-level simulator. The proposed results show the accuracy and simulation time for each description level.

Keywords

circuit simulation; frequency synthesizers; network synthesis; phase locked loops; transceivers; transistors; ADVance MS simulator; Eldo simulator; RF transceivers; Simulink simulator; block diagram; frequency synthesis; phase locked loop; top-down PLL design; transistor-level simulators; Add-drop multiplexers; Circuit simulation; Design methodology; Frequency synthesizers; Hardware design languages; Phase frequency detector; Phase locked loops; Radio frequency; Transceivers; Voltage-controlled oscillators; Circuit Simulation; Design Methodology; Simulation Software;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE

Conference_Location

Honolulu, HI

ISSN

1529-2517

Print_ISBN

1-4244-0530-0

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2007.380927

Filename

4266475