DocumentCode :
298818
Title :
VLSI implementation of a wavelet image compression technique using replicated coding/decoding cells
Author :
Vega-Pineda, Javier ; Cabrera, Sergio D. ; Yi-Chieh Chang
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., El Paso, TX, USA
Volume :
2
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
1173
Abstract :
In this paper a wavelet based algorithm, its architecture and VLSI implementation for a hierarchical image coding technique is presented. The algorithm is based on a biorthogonal expansion involving a pair of mother wavelets, which are 2D discrete pyramid-shaped versions of the piecewise linear B-spline. The implementation is block oriented and includes a post-processing zerotree coding scheme to obtain further compression. The wavelet transform is computed using a previously designed array of replicated cells. The complementary architecture for the zerotree coding scheme is introduced in this paper
Keywords :
VLSI; data compression; decoding; image coding; splines (mathematics); wavelet transforms; 2D discrete pyramid-shaped versions; VLSI implementation; biorthogonal expansion; complementary architecture; hierarchical image coding technique; mother wavelets; piecewise linear B-spline; post-processing zerotree coding scheme; replicated coding/decoding cells; wavelet image compression technique; Decoding; Discrete wavelet transforms; Image coding; Piecewise linear techniques; Signal analysis; Signal design; Signal processing; Signal processing algorithms; Very large scale integration; Wavelet analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.520353
Filename :
520353
Link To Document :
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