Power-Efficient Decision-Feedback Equalizers for Multi-Gb/s CMOS Serial Links

A decision-feedback equalizer (DFE) can compensate for severe signal distortion due to limited channel bandwidth, but its typical power consumption is too high for some applications. This paper describes three CMOS DFEs which embody different design techniques for improved power efficiency. The first one, with two taps, uses a soft decision technique to reduce the critical path delay of the first feedback tap, so that the analog summers can be operated at low currents. This DFE consumes 4.8 mW at 6 Gb/s. The second one, with one tap, employs speculation to relax the critical timing. Speculation increases the number of parallel data paths, but the power dissipation of each path is kept low by using a single switched-capacitor circuit for both sampling and DFE summation. This DFE consumes 5.0 mW at 6 Gb/s. The third one, with two taps, also employs speculation. High power efficiency (9.3 mW at 7 Gb/s) is achieved by implementing the analog summers as resettable integrators.