Title :
Performance driven technology mapper for FPGAs with complex logic block structures
Author :
Lee, Jun-yong ; Shragowitz, Eugene
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
fDate :
30 Apr-3 May 1995
Abstract :
In this work, a technology-mapping procedure for FPGAs was developed, which takes into consideration multiple objectives while focusing on delay optimization. A constructive heuristic was used to minimize circuit delay and maximize the utility of CLBs. The target architecture of this mapper is Xilinx 4000 series, and a set of MCNC benchmarks was used to test the performance
Keywords :
circuit optimisation; delays; field programmable gate arrays; logic CAD; CLBs; FPGAs; MCNC benchmarks; Xilinx 4000 series; circuit delay; complex logic block structures; constructive heuristic; delay optimization; multiple objectives; performance driven technology mapper; technology-mapping procedure; Equations; Field programmable gate arrays; Length measurement; Logic; Routing; Table lookup; Terminology;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.520364
