A Single-chip DBS Tuner-Demodulator SoC using Discrete AGC, Continuous I/Q Correction and 200MS/s Pipeline ADCs

A digital low-IF satellite TV tuner-demodulator SoC was realized in 0.13 mum CMOS using low power 200 MS/s eight bit pipeline ADCs. A discrete-steps delayed AGC loop using FET switched-resistors resulted in a 10 dB noise figure at max gain and +25 dBm IIP3 at min gain. The image rejection correction is continuously performed in the digital domain using an inverse gain and phase mismatch adjustment. A FFT engine was used for carrier/symbol rate estimation and channel blind scanning. SoC specifications include: 0.2 dB implementation loss, <1.3degrms integrated phase noise,<-50dBc spurs, <0.2s channel acquisition time, 1.2 W power dissipation from a dual 1.8/3.3V supply and 1.8 x 4.8 mm² die area.