Logic reduction in timed asynchronous circuits

In this paper the synthesis of timed asynchronous circuits under the aspect of logic reduction is discussed. We introduce interval based timing constraints resulting from the system environment of such interface circuits into the well-known specification form of asynchronous circuits, called signal transition graphs (STGs). As a novel contribution we propose a method to synthesize the corresponding logic according to interface timing. In a first step, we present an efficient analysis algorithm for this timing model. Then a new synthesis procedure is proposed that exploits the results of the timing analysis in order to produce reduced logic implementations. Synthesis results of timed asynchronous circuit specifications demonstrate the advantages of this approach compared to other methods