Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor

In recent years, enjoying multimedia contents with portable devices become popular. These multimedia processing workloads are too heavy workload for a conventional processor so that current portable devices implement additional dedicated processor for multimedia processing. But we have to left conventional processor to execute OS and miscellaneous processing so that this solution enlarges cost, footprint, and power consumption compared to one chip solution. In this paper, we propose the processor called OROCHI which can execute two instruction sets simultaneously. The processor can execute VLIW instruction set for multimedia processing and conventional instruction set for OS and miscellaneous processing. In this paper, we introduce OROCHI processor which is based on a VLIW pipeline. The processor decodes either of the two instruction sets in its corresponding front end. After that, the processor decomposes and translates the conventional instructions and insert them into available slots in VLIW instructions. By these means, we can successfully unite the two processors of different purposes into one specific processor. As a result, we can reduce hardware cost, footprint, and power consumption to meet the rising demands of portable media processing market.