DocumentCode :
2988323
Title :
Minimum area in wheels [VLSI floorplanning]
Author :
Larrea, María José Gil ; Aramburu, José Miguel Urquijo ; Temiño, José Luis Gutiérrez
Author_Institution :
Fac. de Ingenieria, Univ. de Deusto, Bilbao, Spain
Volume :
2
fYear :
2000
fDate :
2000
Firstpage :
646
Abstract :
Solving the floorplan area optimization problem can be extremely hard, even unworkable. Our contribution, a new algorithm called AWO, is described in this paper. It is focused on wheels, or order five floorplans, and the technique employed consists in eliminating all possibly generated redundant and invalid implementations of blocks with wasted areas, previous to each phase of design. Benchmarks used to analyze the performance of existing algorithms show that AWO leads to the final implementations of the wheel in a shorter time and that it is capable of handling more complex non-slicing floorplans, as it demands less memory
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; AWO algorithm; VLSI layout; complex nonslicing floorplans; floorplan area optimization problem; order five floorplans; Algorithm design and analysis; Circuit topology; Gas insulated transmission lines; Performance analysis; Terminology; Very large scale integration; Wheels;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
Type :
conf
DOI :
10.1109/ICECS.2000.912960
Filename :
912960
Link To Document :
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