A general purpose discrete-time multiplexing neuron-array architecture

The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. The authors propose an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results