A robust parallel delta-sigma A/D converter architecture

This paper presents an A/D converter architecture in which four 4 ^th order ΔΣ modulator channels are operated in parallel at a time-oversampling ratio of 10 to obtain an ideal signal-to-quantization error ratio corresponding to 18-bits. The architecture has the property that any x-bit decrease in individual ΔΣ modulator conversion performance due to non-ideal circuit behavior causes an x+1-bit decrease in the overall A/D conversion performance. The additional error caused by gain and offset mismatches among the four channels is either tolerable or removable using a simple digital compensation scheme. Thus, much of the robustness of ΔΣ modulators is preserved