DocumentCode :
298851
Title :
Rate-optimal static scheduling of DSP data flow graphs onto multiprocessors using circuit contraction
Author :
Shatnawi, Ali ; Ahmad, M.O. ; Swamy, M.N.S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Volume :
2
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
1360
Abstract :
This paper is concerned with the compile-time (static) scheduling of data flow graphs (DFGs) onto multiprocessor systems. It mainly concentrates on producing a rate-optimal time schedule that achieves the minimum iteration period, known as the iteration period bound. A combinatorial theory is developed to produce a rate-optimal time schedule for a fully specified DFG. The DFG is first converted to a critical graph by making all its circuits critical. Next, it is transformed into an acyclic graph through a sequence of circuit contractions. An algorithm is then proposed which achieves the time scheduling of the given DFG by first scheduling the acyclic graph, followed by a scheduling of the critical circuits in an order which is reverse to that of their contraction
Keywords :
IIR filters; data flow graphs; iterative methods; multiprocessing systems; processor scheduling; scheduling; signal processing; DSP data flow graphs; acyclic graph; circuit contraction; combinatorial theory; compile-time scheduling; critical graph; data flow graphs; iteration period bound; minimum iteration period; multiprocessor systems; rate-optimal static scheduling; rate-optimal time schedule; Application software; Circuits; Data flow computing; Delay; Digital signal processing; Flow graphs; IIR filters; Processor scheduling; Scheduling algorithm; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.520399
Filename :
520399
Link To Document :
بازگشت