Highly parallel VLSI architectures for linear convolution

This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom´s algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et al. (1991). The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only