Title :
Highly efficient multi-point clock distribution networks
Author :
Aguiar, Rui L. ; Santos, Dinis M.
Author_Institution :
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Abstract :
This paper presents techniques for top-level high-speed clock distribution in large VLSI circuits. The techniques described resort to feedback mechanisms on the clock path, using controlled delay lines. These techniques allow the synchronization of a large number of top-level domains without extra interconnection lines, with clear performance improvements over other proposals
Keywords :
VLSI; circuit feedback; clocks; delay lines; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; VLSI circuits; clock path; controlled delay lines; feedback mechanisms; interconnection lines; multi-point clock distribution networks; top-level domains; top-level high-speed clock distribution; CMOS technology; Clocks; Delay lines; Feedback; Integrated circuit interconnections; Jitter; Repeaters; Synchronization; Telecommunications; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
DOI :
10.1109/ICECS.2000.913002
