A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area

We describe the implementation of a 128×128 crossbar switch in 90 nm CMOS standard-cell ASIC technology. The crossbar operates at 750 MHz and is 32-bits for a port capacity above 20Gb/s, while fitting in a silicon area as small as 6.6 mm² by filling it at the 90% level (control not included). Next, we arrange 128 1 mm² "user tiles" around the crossbar, forming a 150 mm² die, and we connect all tiles to the crossbar via global links that run on top of SRAM blocks that we assume to occupy three fourths of each user tile. Including the overhead of repeaters and pipeline registers on the global links, the area cost of the crossbar is 6% of the total tile area. Thus, we prove that crossbars are dense enough and can be connected "for free" for valencies exceeding by far the few tens of ports, that were believed to be the practical limit up to now, and reaching above one hundred ports. Applications include Combined Input-Qutput Queued switch chips for Internet routers and data-center interconnects and the replacement of mesh-type NoC for many-core chips.