DocumentCode :
2989279
Title :
Stress analysis of interconnect structure in COF by finite element method
Author :
Peng, Yaowei ; Wang, Z.P. ; Chan, Justy ; Xiao, Fei
Author_Institution :
Dept. of Mater. Sci., Fudan Univ., Shanghai, China
fYear :
2003
fDate :
28-30 Oct. 2003
Firstpage :
76
Lastpage :
81
Abstract :
Stress analysis is of crucial importance in the process development of non-conductive film (NCF) and Au-Au thermo-compression bonding for chip on foils. In this paper, the authors present the finite element simulation results of chip on foil process with emphasis on the effect of interconnect structure, in particular on the stresses in the Al layer in the IC pads. Track width and misalignment were two main factors studied. The former affects the foil and interconnect design; while the later is related to manufacturing tolerance and bonding machine accuracy. It is shown that the bonding force, track width and misalignment have great influence on the, maximum stress in the aluminum layer of the IC bonding pads. The simulation results are compared with the experiments. Good agreement on the crack location was demonstrated.
Keywords :
electronics packaging; fine-pitch technology; finite element analysis; foils; gold; lead bonding; stress analysis; Au-Au; IC pads; bonding machine accuracy; chip on foil; crack location; fine pitch; finite element method; interconnect structure; manufacturing tolerance; nonconductive film; polyimide foil; stress analysis; thermocompression bonding; track misalignment; track widths; Aluminum; Artificial intelligence; Bonding forces; Bonding processes; Curing; Finite element methods; Gold; Insulation life; Temperature; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology Proceedings, 2003. ICEPT 2003. Fifth International Conference on
Conference_Location :
Shanghai, China
Print_ISBN :
0-7803-8168-8
Type :
conf
DOI :
10.1109/EPTC.2003.1298696
Filename :
1298696
Link To Document :
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