A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process

Author

Zarei, Hossein ; Shoaei, Omid ; Fakhraie, S.M. ; Zakeri, M.M.

Author_Institution

Dept. of ECE, Tehran Univ., Iran

Volume

2

fYear

2000

fDate

2000

Firstpage

887

Abstract

A 1.4 GHz programmable divider, whose modulus can be varied from 16 to 31 is presented with improved timing of multi-modulus divider structure and high-speed low-voltage embedded logic D-flip flop. Programmability is achieved by gating the feedback signal of the first latch of the divide-by-2 blocks. For high-speed operation, the first control stage, is implemented with a simple pseudo-NMOS logic gate. The programmable divider has been simulated in a 0.6 μm digital CMOS technology with 13 mW consumption at 2.7 V power supply and 1.4 GHz maximum frequency

Keywords

CMOS digital integrated circuits; digital radio; flip-flops; frequency dividers; high-speed integrated circuits; low-power electronics; programmable circuits; timing; 0.6 micron; 1.4 GHz; 13 mW; 2.7 V; DRRS standard; digital CMOS technology; digital radio relay systems; divide-by-2 blocks; embedded AND gate; embedded logic D-flip flop; high-speed D-flip flop; high-speed operation; latch feedback signal gating; low-voltage D-flip flop; multi-modulus divider structure; programmable frequency divider; pseudo-NMOS logic gate; timing; variable modulus; CMOS logic circuits; CMOS process; CMOS technology; Circuit synthesis; Delay effects; Delta-sigma modulation; Energy consumption; Frequency conversion; Logic circuits; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.913018

Filename

913018