DocumentCode
2989942
Title
Loop unrolling minimisation in the presence of multiple register types: A viable alternative to modulo variable expansion
Author
Bachir, Mounira ; Brault, Frederic ; Touati, Sid-Ahmed-Ali ; Cohen, Albert
Author_Institution
INRIA Saclay - Ile de France, Orsay, France
fYear
2011
fDate
4-8 July 2011
Firstpage
207
Lastpage
214
Abstract
Modulo Variable Expansion (MVE) [1] used with software pipelining (SWP) may sacrifice the register optimality (MAXLIVE) and in general may lead to unnecessary spills or move operations negating the benefits of SWP. In con trast, bigger loop unrolling can be performed to meet the MAXLIVE registers requirement [2, 3]. However, the degree of unrolling should be minimised to control code size and hence I-cache performance. In our previous work, we designed a post-pass unrolling algorithm which minimises the unrolling degree while adjusting the length of reuse circuits through the usage of additional (free) registers [4]. In this paper, we complete our study with an improved algorithm for minimising kernel loop unrolling resulting from cyclic register allocation in the presence of multiple register types showing that considering all register types in conjunction provides a lower unrolling degree than considering each register type in isolation. In addition, we integrate our solution within a real world embedded system compiler: st200cc for the ST2xx family of VLIW embedded processors and compare it to MVE. Our large set of experiments on both high performance and embedded benchmarks (SPEC2000, SPEC2006, MEDIABENCH and FFMPEG) demonstrates the practical applicability and the benefits of our approach.
Keywords
optimising compilers; pipeline processing; program control structures; FFMPEG benchmark; MAXLIVE registers requirement; MEDIABENCH benchmark; MVE; SPEC2000 benchmark; SPEC2006 benchmark; ST2xx family; SWP; VLIW embedded processors; cyclic register allocation; embedded system compiler; kernel loop unrolling minimisation; modulo variable expansion; multiple register types; register optimality; software pipelining; st200cc; Kernel; Minimization; Pipeline processing; Program processors; Registers; Resource management; Code Optimisation; Code Size Reduction; ILP; Software Pipelining;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing and Simulation (HPCS), 2011 International Conference on
Conference_Location
Istanbul
Print_ISBN
978-1-61284-380-3
Type
conf
DOI
10.1109/HPCSim.2011.5999826
Filename
5999826
Link To Document