Title :
Leakage Minimization of Single-Phase Register File Based on Two-Phase CPAL Using MTCMOS
Author :
Sheng, Xiaolei ; Hu, Jianping
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
With the development of CMOS technology and the decrease of threshold voltage, leakage current increases drastically so that it cannot be ignored in low-power design. MTCMOS (Multi-Threshold CMOS) power-gating scheme has been proven as an effective way to reduce leakage consumption during sleep mode. This paper presents a MTCMOS power-gating scheme for an adiabatic register file based on two-phase CPAL (complementary pass-transistor adiabatic logic) circuits, which can operate in a single-phase power clock by introducing a two-phase power-clock generator. A 32×32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulations show that the leakage losses are greatly reduced.
Keywords :
CMOS logic circuits; clocks; leakage currents; low-power electronics; MTCMOS power gating scheme; complementary pass transistor adiabatic logic; leakage current; leakage minimization; low power design; multithreshold CMOS; single phase adiabatic register file; single phase power clock; two phase CPAL; two phase power clock generator; Clocks; Energy loss; Generators; Registers; Switching circuits; Threshold voltage; Transistors; MTCMOS; complementary pass-transistor adiabatic logic; leakage reduction; register file;
Conference_Titel :
Electrical and Control Engineering (ICECE), 2010 International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-6880-5
DOI :
10.1109/iCECE.2010.1469
