Leakage Minimization of Single-Phase Register File Based on Two-Phase CPAL Using MTCMOS

With the development of CMOS technology and the decrease of threshold voltage, leakage current increases drastically so that it cannot be ignored in low-power design. MTCMOS (Multi-Threshold CMOS) power-gating scheme has been proven as an effective way to reduce leakage consumption during sleep mode. This paper presents a MTCMOS power-gating scheme for an adiabatic register file based on two-phase CPAL (complementary pass-transistor adiabatic logic) circuits, which can operate in a single-phase power clock by introducing a two-phase power-clock generator. A 32×32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulations show that the leakage losses are greatly reduced.