A proposal for very high performance FFT processor architectures

A method for designing highly efficient and very high performance FFT processors is presented. The paper examines the problem of optimally allocating the operations of an FFT computation to pipelined architectures of processing elements, including the trade-offs associated with the data transfer operations to support the processing. The problem of balancing of processing power of the individual components with the intrinsic constraints imposed by pin limitations, is also examined.