Vertical 3D interconnect through aligned wafer bonding

Wafer-to-wafer chip stack technologies offer an approach to interconnect two integrated circuits for the purpose of shortening the wiring between them. With this 3D interconnect solution, increasing device functional density and reducing total packaging costs are focused on. Wafers are aligned, bonded and the interlayer is connected electrically, and then thinned-back, prior to dicing. High precision wafer alignment and subsequent thermo-compression bonding, to form the electrical interconnects, are considered as a key enabling technology for 3D interconnect. In this article, the current status of wafer alignment and wafer bonding as well as integration in high-volume production environments is analyzed. As the success of this technology is highly dependent on the alignment accuracy of wafers face-to-face below 1 /spl mu/m, a high emphasis lies in the capability of the process equipment, which must cover the special needs of 3D interconnect technology, such as high accuracy, the use of single side processed wafers, and 300 mm wafer capability.