Title :
Soft IP Integration and Reuse Challenges in Intel Entry Level Network Processor
Author :
Wai Mun Ng ; Kok Sing Yap ; Kean Hong Boey
Author_Institution :
Commun. Infrastructure Group, Intel Microelectron. (M) Sdn. Bhd., Penang, Malaysia
fDate :
Oct. 29 2006-Dec. 1 2006
Abstract :
Often a new product evolves from its predecessors with enhanced performances and added features. To reduce re-development time and effort, IP-based reuse methodology is used. This paper presents the challenges encountered in integrating IPs of multiple sources from two design cases in an Intel-based network processor.
Keywords :
logic design; microprocessor chips; IP-based reuse methodology; Intel entry level network processor; reuse challenges; soft IP integration; Atherosclerosis; Calibration; Investments; Logic; Microelectronics; Registers; Universal Serial Bus;
Conference_Titel :
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-9730-4
DOI :
10.1109/SMELEC.2006.381093
