Two VLSI design advances in arithmetic coding

This paper presents two VLSI design advances for arithmetic coding which is an entropy coding technique for image coding. First, we present an algorithm which has less performance degradation in finite word-length implementation than two previously analyzed algorithms. Second, we propose the implementation of the interval width register update operation using redundant arithmetic to obtain further speed-up in the VLSI implementation of the JPEG/JBIG binary arithmetic coding algorithm known as QM-coder. The resulting hardware design achieves a faster clock rate and can be combined with previously proposed high speed techniques