DocumentCode
2991426
Title
XREF coupling: capacitive coupling error checker
Author
Grundmann, B. ; Yen, Y.T.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
244
Lastpage
247
Abstract
Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.<>
Keywords
CMOS integrated circuits; VLSI; circuit layout CAD; CMOS VLSI circuit; XREF coupling; capacitive coupling error checker; critical nodes; logical operation; pattern-independent circuit verification tool; CMOS digital integrated circuits; CMOS logic circuits; Capacitance; Circuit simulation; Coupling circuits; Design methodology; Humans; Switches; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129892
Filename
129892
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