A 10-Bit 50-MSPS Pipelined CMOS ADC

Author

Hashim, Mohamad-Faizal ; Yusoff, Yuzman ; Ahmad, Mohd Rais

Author_Institution

MIMOS Berhad, Kuala Lumpur

fYear

2006

fDate

Oct. 29 2006-Dec. 1 2006

Firstpage

459

Lastpage

463

Abstract

This paper presents a 10-bit 50-MSPS pipelined ADC targeted to 0.35 um CMOS technology. The main characteristics of pipelined ADC such as signal to noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential non-linearity (DNL), integral non-linearity (INL) and power consumption are simulated in HSPICEreg. In this simulation, a full-scale of Nyquist-frequency sine-wave input is used. The results show the designed pipelined ADC achieves a SNDR of 58 dB, SFDR of 70 dB, maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.5 least significant bit (LSB) and a power consumption of 350-mW.

Keywords

CMOS digital integrated circuits; SPICE; analogue-digital conversion; integrated circuit design; CMOS technology; HSPICE; Nyquist-frequency sine-wave input; differential nonlinearity; distortion ratio; integral nonlinearity; pipelined CMOS ADC; power 350 mW; power consumption; signal-to-noise ratio; size 0.35 mum; spurious free dynamic range; CMOS integrated circuits; CMOS technology; Energy consumption; Error correction; Frequency; Linearity; MIMO; Redundancy; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-9730-4

Electronic_ISBN

0-7803-9731-2

Type

conf

DOI

10.1109/SMELEC.2006.381103

Filename

4266653