A stepwise refinement algorithm for integrated floorplanning, placement and routing of hierarchical designs

This paper presents a stepwise refinement approach to floorplanning, followed by the placement and routing of hierarchical VLSI circuits. The algorithm consists of several traversals of the design hierarchy, from each of which more accurate information about the design is obtained before the actual placement and routing is performed. Interdependencies between different levels of the hierarchy are considered in this approach. The algorithm is capable of being applied to large circuits with many levels of hierarchy and with many modules at each level