DocumentCode
2991719
Title
Data path construction and refinement
Author
Fur-Shing Tsai ; Yu-Chin Hsu
Author_Institution
Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
308
Lastpage
311
Abstract
A system is described for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The actions taken in each phase are described. The authors´ contributions include the following: (1) theorems for the lower bound of the number of interconnections; (2) in the DPR phase, a more global view of the allocation problem is taken by ripping up and reallocating different types of objects simultaneously; (3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; (4) a method to judge the potential for upgrading a data path; and (5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results.<>
Keywords
circuit CAD; digital signal processing chips; STAR; allocation; binding quality; data path allocation; data path construction; data path refinement; digital signal processor synthesis; hardware resources sharing; linear topology; random topology; relation network; Computer science; Control system synthesis; Data structures; Digital signal processors; Hardware; Iterative methods; Resource management; Scheduling; Signal synthesis; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129910
Filename
129910
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