DocumentCode
2991729
Title
Partial scan by use of empirical testability
Author
Kim, Kee S. ; Kime, Charles R.
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
1990
fDate
11-15 Nov. 1990
Firstpage
314
Lastpage
317
Abstract
The objective of the partial scan method proposed is to obtain maximum fault coverage for the number of scan elements selected. Empirical testability difference (ETD), a measure of the potential improvement in the overall testability of the circuit, is used to successively select storage elements for scan. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the actual test sequence generator. In addition, ETD focuses on the hard-to-detect faults rather than all faults once such faults are known. The method has been extensively tested with ten of the sequential circuits given by F. Brglez et al. (1989) using the FASTEST provided by T. Kelsey and K. Saluja (1989). The results of these tests indicate that ETD yields on average either 27% of the number of uncovered faults for the same number of scan elements or 21% fewer scan elements for the same fault coverage compared to the other methods studied.<>
Keywords
automatic testing; fault location; integrated circuit testing; logic testing; FASTEST; empirical testability; empirical testability difference; hard-to-detect faults; maximum fault coverage; partial scan method; sequential circuits; test sequence generator; testability measures; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Controllability; Design for testability; Hardware; Observability; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2055-2
Type
conf
DOI
10.1109/ICCAD.1990.129912
Filename
129912
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