Weak point and improvement of CMOS Schmitt Trigger Circuit used in Microcontroller about ND-mode ESD

Author

Jeong, Jae-Seong ; Lee, Jung-Min ; Park, Sang-Deuk

Author_Institution

CS Manage. Center, Suwon

fYear

2006

fDate

Oct. 29 2006-Dec. 1 2006

Firstpage

558

Lastpage

561

Abstract

In this study, We investigated weak point and improvement about ND-mode ESD of CMOS Schmitt trigger circuit embeded in Microcontroller. Junction spiking conditions on NMOS of the CMOS Schmitt trigger circuit were Vcc Common mode, ND-mode 1.4 kV, and 0.8-1.2 sec zap interval (pin to pin). Failure mechanism by LNPN action formed in CMOS Schmitt trigger circuit was reproduced. We have identified Root Cause and improved circuits to achieve ESD damage free.

Keywords

CMOS digital integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit testing; microcontrollers; trigger circuits; CMOS Schmitt trigger circuit; ESD damage free circuits; ND-mode ESD; Vcc Common mode; electrostatic discharge; failure mechanism; microcontroller; no defect failure mode; time 0.8 s to 1.2 s; voltage 1.4 kV; Biological system modeling; Circuit testing; Clocks; Earth Observing System; Electrostatic discharge; Failure analysis; Integrated circuit reliability; MOS devices; Microcontrollers; Trigger circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

0-7803-9730-4

Electronic_ISBN

0-7803-9731-2

Type

conf

DOI

10.1109/SMELEC.2006.380693

Filename

4266676