DocumentCode
2992121
Title
High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling´s Algorithm
Author
Lakshmanan ; Meaamar, Ali ; Othman, Masuri
Author_Institution
Univ. Kebangsaan Malaysia, Bangi
fYear
2006
fDate
Oct. 29 2006-Dec. 1 2006
Firstpage
598
Lastpage
602
Abstract
Parallel-prefix adders offer high efficiency solution in terms of area, speed, power and regularity to the binary addition problem and are well suited for VLSI implementation. In this paper, a novel technique of implementing a hybrid parallel- prefix ling adder is presented. Experimental results show that the proposed adder has an improvement of 63% in speed and about 13% reduction in power consumption compared to Carry Lookahead adder (CLA).
Keywords
VLSI; adders; carry logic; Ling´s algorithm; VLSI implementation; binary addition problem; carry lookahead adder; high-speed hybrid parallel-prefix carry-select adder; power consumption; Adders; Algorithm design and analysis; Application specific integrated circuits; Design engineering; Encoding; Hardware design languages; Libraries; Power engineering and energy; Signal processing algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on
Conference_Location
Kuala Lumpur
Print_ISBN
0-7803-9730-4
Electronic_ISBN
0-7803-9731-2
Type
conf
DOI
10.1109/SMELEC.2006.380702
Filename
4266685
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