Title :
VLSI Architecture for a one chip video median filter
Author_Institution :
ENST, Paris Cedex, France
Abstract :
Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.
Keywords :
Circuits; Clocks; Computer architecture; Data flow computing; Data mining; Parallel processing; Pixel; Systolic arrays; Throughput; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
DOI :
10.1109/ICASSP.1985.1168243
