DocumentCode :
299224
Title :
Neural network based estimation of VLSI building block dimensions from schematics
Author :
Li, Xiao Quan ; Jabri, Marwan A.
Author_Institution :
Dept. of Electr. Eng., Sydney Univ., NSW, Australia
Volume :
1
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
381
Abstract :
The estimation of the height and width of a custom cell layout (CCL) from schematics is an important task in integrated circuit computer aided design and can be of direct assistance to designers. In this paper, we describe and report results on two CCL dimension estimation techniques. In the first, a neural network is trained to predict the width (or height) of a cell given its schematics and its height (or width). The results show that knowledge of one dimension significantly improves the prediction accuracy of the other. In the second, we explore improvements to previous work (see IEEE Trans. on Neural Networks, vol. 3, no. 1, p. 146-153, 1992) on simultaneous CCL dimension prediction by replacing the neural network that estimates the width and height simultaneously by cascaded neural networks
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; neural nets; CAD; VLSI building block dimensions; cascaded neural networks; computer aided design; custom cell layout; dimension estimation techniques; integrated circuit design; neural network based estimation; schematics; Australia; Design methodology; Electronics packaging; Integrated circuit layout; Integrated circuit synthesis; Neural networks; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.521530
Filename :
521530
Link To Document :
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