Title :
Hardware realization of concise evolutionary algorithm on FPEA
Author :
Yan, Shengli ; Chen, Yue ; Pu, Qingmin
Author_Institution :
Dept. of Electron. Inf. Eng., Zhongshan Polytech., Zhongshan, China
Abstract :
Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard concise evolutionary algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for realization, the architecture processing speed and the solving power of the CEA for evolutionary hardware.
Keywords :
evolutionary computation; field programmable gate arrays; integrated circuit design; logic design; FPEA; FPGA; architecture processing speed; block diagram design; concise evolutionary algorithm; data flow design; embedded logic projects; evolutionary hardware; hardware realization; logical blocks; probability vector; Bioinformatics; Evolutionary computation; Genetic mutations; Genomics; Hardware; Logic; Power engineering and energy; Process design; Evolutionary Algorithm; Evolutionary Hardware; FPEA;
Conference_Titel :
Computer-Aided Industrial Design & Conceptual Design, 2009. CAID & CD 2009. IEEE 10th International Conference on
Conference_Location :
Wenzhou
Print_ISBN :
978-1-4244-5266-8
Electronic_ISBN :
978-1-4244-5268-2
DOI :
10.1109/CAIDCD.2009.5374864
