Title :
Challenges & solutions in the die attach process for micro thin die
Author :
Siew Han Looe ; Soon Wei Wang
Author_Institution :
ON Semiconductor, Lot 122, Senawang Industrial Estate, 70450 Seremban, NSDK, West Malaysia, Malaysia
Abstract :
The drive for package thickness thinning and package size reduction has created new challenges for current wafer fabrication and assembly technology which has led to the smaller die and thinner wafer thickness trend. Thus, the conventional wafer thickness of 8 mils decreases to 4 mils is more challenging for the new innovation package of Micro Leadless Land Grid Array (µLLGA) with only 0.4mm package thickness.
Keywords :
Assembly; Copper; Fabrication; Lead; Microassembly; Semiconductor device packaging; Substrates; Textile industry; Tiles; Wafer bonding;
Conference_Titel :
Electronic Manufacturing Technology Symposium (IEMT), 2008 33rd IEEE/CPMT International
Conference_Location :
Penang, Malaysia
Print_ISBN :
978-1-4244-3392-6
Electronic_ISBN :
1089-8190
DOI :
10.1109/IEMT.2008.5507793