Title :
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Abstract :
The following topics were covered: device/circuit co-designing for advanced technologies; system level specification and simulation; BDD and sequential verification issues; interconnect design optimisation; design for manufacturability; system-level design; equivalence checking; parasitic extraction and reduced order models; functional decomposition and PLA-based logic synthesis; low power techniques for embedded software; asynchronous system design - architecture and low-power; analog design methodology; low power design methodology; advanced BIST; DSM design and analysis; signal integrity and analysis; design experiments for mobile applications; compilation techniques for embedded software; asynchronous system design - synthesis; system level power optimisation; multi-level logic optimization for logic circuits; practical and high level DFT; performance driven floorplaning and placement; delay and power estimation improvement; networked reconfiguration and systems; advances in timing optimisation of logic circuits; logic synthesis for low power and design space exploration; optimisation techniques for FPGAs; processor synthesis
Keywords :
VLSI; analogue integrated circuits; asynchronous circuits; built-in self test; circuit CAD; circuit layout CAD; circuit optimisation; circuit simulation; design for manufacture; digital integrated circuits; high level synthesis; integrated circuit design; logic CAD; low-power electronics; monolithic integrated circuits; BIST; DSM design; FPGA; IC design automation; PLA-based logic synthesis; analog design methodology; asynchronous system design; codesigning; compilation techniques; delay estimation; design space exploration; embedded software; equivalence checking; high level DFT; interconnect design optimisation; low power design methodology; multilevel logic optimization; parasitic extraction; performance driven floorplaning; performance driven placement; power estimation; processor synthesis; sequential verification; signal integrity; system level simulation; system level specification; timing optimisation;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913257
