• DocumentCode
    2992703
  • Title

    A vector-pipeline DSP for low-rate videophones

  • Author

    Kobayashi, K. ; Eguchi, M. ; Iwahashi, T. ; Shibayama, Takashi ; Li, X. ; Taka, K. ; Onodera, H.

  • Author_Institution
    Graduate Sch. of Inf., Kyoto Univ., Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We propose a vector-pipeline processor VP-DSP for low-rate videophones, which can encode and decode 10 frames/s of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 μm CMOS process. The area of the VP-DSP core is 4.2 mm2 works properly at 25 MHz/1.6 V with the power dissipation of 49 mW. Its peak performance is up to 400 MOPS, 8.2 GOPS/W
  • Keywords
    CMOS digital integrated circuits; VLSI; data compression; decoding; digital communication; digital signal processing chips; pipeline processing; real-time systems; vector processor systems; video coding; videotelephony; 0.35 micron; 1.6 V; 25 MHz; 29.2 kbit/s; 49 mW; CMOS process; decoding; encoding; low-rate videophones; vector-pipeline DSP; vector-pipeline processor; Concurrent computing; Decoding; Digital signal processing; Discrete cosine transforms; Image coding; Informatics; Large scale integration; Pipelines; Registers; Vector quantization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-6633-6
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2001.913259
  • Filename
    913259
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2992703