Title :
Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs
Author :
Winzker, Marco ; Pirsch, Peter ; Reimers, Jochen
Author_Institution :
Lab. fur Informationstechnol., Hannover Univ., Germany
fDate :
30 Apr-3 May 1995
Abstract :
The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible
Keywords :
DRAM chips; decoding; high definition television; television standards; video coding; MPEG2 HDTV-decoders; architecture requirements; hierarchical transmission; memory requirements; stand-alone transmission; synchronous DRAMs; Clocks; Decoding; Degradation; Delay; Laboratories; Mass production; Memory architecture; Noise reduction; Transform coding; Video compression;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.521587
