Title :
Multi-hit time-to-digital converter VLSI for high-energy physics experiments
Author_Institution :
Inst. of Particle & Nucl. Studies, Nat. High Energy Accelerator Res. Organ., Tsukuba, Japan
Abstract :
A multi-hit time-to-digital converter VLSI has been developed using a CMOS 0.3 μm gate-array technology. The chip is designed for use in a high-energy physics experiment ATLAS. Precise timing signals are generated from 16 taps of an asymmetric ring oscillator oscillating at 80 MHz and controlled by a PLL circuit. A prototype chip has been developed, and a time resolution of 300 ps RMS was obtained. Many macro cells are developed to achieve such high resolution still using commercial gate-array technology
Keywords :
CMOS integrated circuits; VLSI; analogue-digital conversion; cellular arrays; colliding beam accelerators; nuclear electronics; phase locked loops; timing; 0.3 micron; 80 MHz; ATLAS; CMOS gate-array technology; PLL circuit; VLSI; asymmetric ring oscillator; high-energy physics experiment; macro cells; multi-hit time-to-digital converter; prototype chip; time resolution; timing signals; CMOS technology; Circuits; Phase locked loops; Physics; Prototypes; Ring oscillators; Signal generators; Signal resolution; Timing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913261
