High-speed FIR digital filter with CSD coefficients implemented on FPGA

Author

Yamada, Mitsuru ; Nishihara, Akinori

Author_Institution

Graduate Sch. of Sci. & Eng., Tokyo Inst. of Technol., Japan

fYear

2001

fDate

2001

Firstpage

7

Lastpage

8

Abstract

A very fast and low-complexity FIR digital filter on FPGA is presented. Multipliers in the filter whose coefficients are expressed as canonic signed digit (CSD) code are realized with wired-shifters, adders and subtracters. The critical path is minimized by insertion of pipeline registers and is equal to the propagation delay of an adder. The number of pipeline registers is limited by using an equivalent transformation on a signal flow graph. The price paid for the 100% speedup is 5% increase in the area. The maximum sampling frequency is 78.6 MHz

Keywords

FIR filters; adders; delays; digital filters; field programmable gate arrays; high-speed integrated circuits; pipeline processing; signal flow graphs; 78.6 MHz; CSD coefficients; FPGA; adders; canonic signed digit; equivalent transformation; high-speed FIR digital filter; pipeline registers; propagation delay; sampling frequency; signal flow graph; subtracters; wired-shifters; Added delay; Adders; Digital filters; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Logic; Pipeline processing; Propagation delay; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913262

Filename

913262