DocumentCode
2992882
Title
Implications of cache asymmetry on server consolidation performance
Author
Apparao, Padma ; Iyer, Ravi ; Newell, Don
Author_Institution
Hardware Archit. Lab., Intel Corp., Santa Clara, CA
fYear
2008
fDate
14-16 Sept. 2008
Firstpage
24
Lastpage
32
Abstract
Todaypsilas CMP platforms are designed to be symmetric in terms of platform resources such as shared caches. However, it is becoming increasingly important to understand the performance implications of asymmetric caches for two key reasons: (a) multi-workload scenarios such as server consolidation are a growing trend and contention for shared cache resources between workloads causes logical cache asymmetry, (b) future CMP platforms may be designed to be physically asymmetric in hardware due to die area pressure, process variability or power/performance efficiency. Our focus in this paper is to understand the performance implications of both logical as well as physical asymmetric caches on server consolidation. Based on real measurements of a state-of-the-art CMP processor running a server consolidation benchmark (vConsolidate) we compare the performance implications as a function of (a) symmetric caches, (b) virtually asymmetric caches, (c) physically asymmetric caches and (d) a combination of logically and physically asymmetric caches. We analyze the performance behavior in terms of (i) performance of each of the individual workloads being consolidated and (ii) architectural components such as CPI and MPI. We believe that this asymmetric cache study is the first of its kind and provides useful data/insights on cache characteristics of server consolidation. We also present inferences on future optimizations in the VMM scheduler as well as potential hardware techniques for future CMPs with cache asymmetry.
Keywords
cache storage; file servers; microprocessor chips; virtual machines; chip multiprocessor platform; logical cache asymmetry; multi workload scenario; physical asymmetric cache; server consolidation performance; shared cache resource; virtual asymmetric cache; virtual machine performance; Enterprise resource planning; Hardware; Java; Laboratories; Multicore processing; Performance analysis; Potential well; Processor scheduling; Sockets; Virtual machining;
fLanguage
English
Publisher
ieee
Conference_Titel
Workload Characterization, 2008. IISWC 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-2777-2
Electronic_ISBN
978-1-4244-2778-9
Type
conf
DOI
10.1109/IISWC.2008.4636088
Filename
4636088
Link To Document