High-level estimation of high-performance architectures for Reed-Solomon decoding

Reed-Solomon (RS) codes are a standard error-detection and correction approach in diverse communication and computer systems. The major obstacle to wider application has been a computationally complex decoding structure not native to conventional languages and microprocessors due to finite field arithmetic. Based on our previous work on finite field arithmetic, this paper shows a detailed computational structure of RS decoding algorithms, which are expressed by parallel hardware implementations using an array synthesis method. The purpose of this paper is to explore detailed computational structures of the RS decoder as a purely parallel implementation and make high level estimations on area and performance without actually building hardware. Depending on design criteria, we can then apply various mapping strategies to obtain a set of implementations which satisfy a broad range of performance, cost, power and reliability requirements