Design and implementation of JPEG encoder IP core

Author

Lian, Chung-Jr ; Chen, Liang-Gee ; Chang, Hao-Chieh ; Chang, Yung-Chi

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2001

fDate

2001

Firstpage

29

Lastpage

30

Abstract

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-μm single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc

Keywords

application specific integrated circuits; circuit CAD; data compression; image coding; industrial property; integrated circuit design; 0.6 micron; 3.3 V; 40 MHz; COMPASS cell library; JPEG encoder IP core; TSMC; application systems; pipelined architecture; run-time reconfigurable quantization tables; single-poly triple-metal process; soft IP; Delay; Digital cameras; Discrete cosine transforms; Hardware; Image coding; Image storage; Quantization; Read-write memory; System-on-a-chip; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913273

Filename

913273