Title :
A real-time 64-monosyllable recognition LSI with learning mechanism
Author :
Nakamura, Kazuhiro ; Zhu, Qiang ; Maruoka, Shinji ; Horiyama, Takashi ; Kimura, Shinji ; Watanabe, Katsumasa
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
In the paper, a real-time 64-mono-syllable recognition LSI is presented. The LSI accepts 11.6 ms speech frame and outputs a 6-bit symbol-code for each frame by the end of the next frame in a pipelining manner. The recognition method is based on the Hidden Markov Model (HMM) and is speaker-independent. An on-chip learning mechanism has also been designed, but the circuit is off-chip for the present implementation because of the restriction of LSI area. The LSI is fabricated by VDEC Rohm with a 0.6 μm CMOS process on a 4.5 mm×4.5 mm chip
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; hidden Markov models; learning (artificial intelligence); linear predictive coding; pipeline processing; real-time systems; speech coding; speech recognition equipment; vector quantisation; 0.6 micron; 64-monosyllable recognition LSI; CMOS process; DSP chip; HMM; VDEC Rohm; VLSI chip; VQ module; hidden Markov model; onchip learning mechanism; real-time recognition LSI; speaker-independent recognition; Adders; Circuits; Hardware; Hidden Markov models; Large scale integration; Learning systems; Linear predictive coding; Speech analysis; Speech coding; Speech recognition;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913274
