DocumentCode :
2993058
Title :
An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter
Author :
Teymourzadeh, Rozita ; Othman, Masuri Bin
Author_Institution :
Univ. Kebangsaan Malaysia, Bangi
fYear :
2006
fDate :
Oct. 29 2006-Dec. 1 2006
Firstpage :
811
Lastpage :
815
Abstract :
The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the subcomponent in the over sampling technique. The design of three main units in the decimation stage that is the cascaded integrator comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.
Keywords :
comb filters; hardware description languages; silicon; CIC; VLSI implementation; Verilog HDL code; Virtex II FPGA board; chip implementation; decimation process; fast cascaded integrator comb filter; power consumption; sampling technique; silicon; Band pass filters; Delta-sigma modulation; Digital filters; Filtering; Frequency response; Hardware design languages; Nanoelectronics; Sampling methods; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Electronics, 2006. ICSE '06. IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
0-7803-9730-4
Electronic_ISBN :
0-7803-9731-2
Type :
conf
DOI :
10.1109/SMELEC.2006.380749
Filename :
4266732
Link To Document :
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