Leakage Reduction of DTGAL Circuits with MTCMOS Power-Gating

Reduction in leakage dissipations has become an important concern in low power and high performance applications. MTCMOS (Multi-Threshold CMOS) power-gating scheme has been proven as an effective way to reduce leakage power consumption during sleep mode. This paper investigates leakage reduction of adiabatic circuits with power-gating schemes using MTCMOS under deep submicron process. The power consumptions of DTGAL (dual transmission gate adiabatic logic) circuits using MTCMOS power-gating scheme are investigated in different processes, frequencies and active ratios. All circuits are verified using HSPICE, and BSIM4 model is adopted to reflect the leakage currents. HSPICE simulations show that the leakage losses are greatly reduced by using the DTGAL power-gate techniques with MTCMOS.